Hi,

I previously posted a similar question on OPENRISC. But I thought here is where I must ask my question. Apologies if you see the post twice:

I synthesized MINSOC on TSMC 180nm technology (design compiler). The area is about 5.5mm*5.5mm (OR1200 core: 2.5mm*2.5mm. The other part of the area is used for JTAG, RAM, Debugger,...). I think it is very large (or am I wrong?). I used generic implementations wherever required and synthesis seems correct. Does anyone here have any information about the area of an ASIC implementation of MINSOC on 180nm or any other technologies?